1. Field of the Invention
The present invention relates to a successive approximation register (SAR) analog-digital converter (ADC). In particular, the present invention relates to a SAR ADC capable of performing correction on an error code that is generated during operation, and a method of driving the same.
2. Discussion of Related Art
A successive approximation register (SAR) analog-digital converter (ADC) includes a binary capacitor array, a comparator, and a controller, and converts an analog voltage into a digital signal during a sample mode and a hold mode.
The current SAR ADC is highlighted in a region having a resolution of 8 to 16 bits and a conversion rate of 5 to 100 MS/s. The SAR ADC is on the rise as a next-generation data converter with high-efficiency due to its low electric power consumption.
Despite its advantages, the SAR ADC fixes an input, and searches for a digital output that is the closest to the input by successively changing a reference voltage, so that an error is generated during the conversion.
When an error occurs in the SAR ADC, it cannot be corrected. That is, although a desired digital code is 10100, when D2 code outputs a value of 0 for whatever reason, a general SAR ADC outputs a digital code of 10011. Once a digital bit is determined, correction thereof is not possible, and thus lower order bits may be given an effect.